Error detection, isolation and recovery apparatus for a multiprocessor array

摘要

A central controlling microprocessor interfaces over commonly connected address and data busses to a plurality of peripheral microprocessors. A memory mapped I/O interface controls access to and from the busses for mutual receipt and exchange of signals between the microprocessors and mutual exchange and receipt of data among the microprocessors. The individual microprocessors are selectively isolatable by a plurality of three state switch means connected between each microprocessor and the interconnecting data and address busses. Error detection and control logic is connected via control lines to the individual microprocessors and responsive to an error indication thereof, activates a multipoint error signal to all said microprocessors over a control line, which signal is interpreted by the microprocessor then controlling said busses as a signal to deactivate its operation and as a signal at said control microprocessor to invoke an interrupt for analyzing the causes of said error. The control microprocessor can issue memory mapped I/O instructions to the individual three state selective isolation means and/or to any of the I/O microprocessors to respectively isolate the microprocessors from said busses or to control said microprocessors in an error analysis routine. The apparatus further includes a machine check register and a bus master register associated with said control microprocessor which registers can be written in by said control microprocessor and read from only by one of said I/O microprocessors.