Domino-type MOS logic gate having an MOS sub-network

摘要

The invention relates to a logic MOS gate of the domino type, having a precharging transistor, a validation transistor and logic transistors. To prevent unwanted discharging of a precharged high level, which may be induced by at least one input data being stabilized too slowly, that is to say not before a clock signal has risen to the high level, a p-MOS sub- network is arranged in parallel with the source-drain path of the precharging transistor and receives at least the input data which was too slowly stabilized in such a manner as to establish a conductor path which reestablishes the precharged high level.