Programmable circuit has sub-networks alternately formed in microchip common plane so logic blocks of one lie in gaps in another; sub-networks are connected at network edges

摘要

The circuit has several logic elements with at least two data inputs and a data output, logic blocks with logic elements connected circularly, network meshes, each with at least 3 circular blocks and a logic network with sub-networks, each containing network meshes. Sub-networks are alternately formed in a common plane of an IC so logic blocks of one sub-network lie in gaps in another. Sub-networks are interconnected at the network edges. The circuit has several logic elements (1) with at least two data inputs (3,4) and a data output (5), several logic blocks (2) with logic elements connected circularly, a number of network meshes, each with at least three circular blocks and a logic network with sub-networks, each containing a number of network meshes. The sub-networks are alternately formed in the a common plane of a microchip so that the logic blocks of one sub-network lie in the gaps in another and the sub-networks are connected together at the network edges.