PURPOSE:To improve the execution performance of a whole processing system by positioning a register file as the cache of a permanent variable and allocating a temporary variable to one part of the cache. CONSTITUTION:An additional processor 2 is activated from a main processor 1, and the additional processor 2 sequentially reads and executes a prolog exclusive instruction in a main memory unit 3. The allocation of the variable at the time of executing a prolog language is allocated not only in a frame on a stack 31 constructed in the main memory 3 but also in a register file 224 in the additional processor 2 which can execute high-speed access. Further, even with respect to the variable allocated in the frame, as much as possible, a variable access instruction, which can access the register file 224 on which the copy is placed, is outputted with a compiler. Thus, the number of times of accessing the main memory is decreased, and the prolog language can be executed at a high speed.
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