INTERRUPTION CONTROLLING SYSTEM FOR DUPLEX PROCESSOR

摘要

PURPOSE:To continue the processing by one processor when the other processor stops operation due to a fault and to improve the reliability of the system by providing each processor with plural input terminals in correspondence to interruption levels of first and second groups different in priority levels. CONSTITUTION:Each of the processors 1A and 1B constituting the system is provided with input terminals 4A and 4B to which interruption signals FIRQA and QB of the first level are inputted, and with those 5A and 5B to which interruption signals IRQA and QB are inputted. To this bus between a bus change-over 2 that is connected to the processors 1A and 1B, and a storage 3, each of resettable FFs 6 and 7 are connected. By the logic of the output from each of the FFs 6 and 7 and various interruption signals, the interruption signals FIRQA and QB, and ones IRQA and QB of the first and second levels respectively, are outputted and supplied to each of the input terminals 4A, 4B and 5A, 5B. In such a way, when either one of the processors 1A and 1B is stopped due to a fault, the other one continued the processing.