DESIGNS AND PROCEDURES FOR TESTING INTEGRATED CIRCUITS CONTAINING SENSOR ARRAYS

摘要

PCT No. PCT/GB90/01451 Sec. 371 Date Apr. 23, 1992 Sec. 102(e) Date Apr. 23, 1992 PCT Filed Sep. 20, 1990 PCT Pub. No. WO91/04498 PCT Pub. Date Apr. 4, 1991.The design and testing of integrated circuits in wafer form for production faults, in the absence of irradiation, is described. This is achieved by fabricating test circuits on each wafer at the periphery of the sensor array. In a preferred arrangement, two test circuits are fabricated on each wafer; one for testing the word lines and the other for testing the bit lines and individual sensing sites. The test circuits are controlled by external signals to input predetermined patterns of data to the array and the array output patterns are compared with the input patterns to assess the level of production faults.