TESTABLE INTEGRATED CIRCUIT, INTEGRATED CIRCUIT DESIGN-FOR-TESTABILITY METHOD, AND COMPUTER-READABLE MEDIUM STORING A PROGRAM FOR IMPLEMENTING THE DESIGN-FOR-TESTABILITY METHOD

摘要

Methods and means are provided for testing an integrated circuit, including a controller or other sequential circuit, at a real operating speed while minimizing the length of the test sequence and achieving high failure coverage. The state of the state register is presumably controllable and observable, and a set of test patterns is obtained for a combinational circuit that does not include the state register. The invalid state generation logic circuit is added to generate the invalid state, and this state is included in the generated test pattern, but can not be set by a normal transition from the reset state. A multiplexer for selecting the next state generating logic circuit or the invalid state generating logic circuit for input to the state register by the state transition mode selecting signal is added. During test generation, the signal corresponding to the pseudo-primary output becomes observable and the multiplexer output signal is detectable externally as the status output signal.