Fully static CMOS cascode voltage switch (CVS) logic circuit

摘要

A static, single-ended cascode voltage switch logic system arranged in a tree with multiple levels. Each level of each branch of the tree is comprised of a complementary pair (10, 12; 22, 24; 26, 28). The system is preferrably implemented in CMOS, so that each complementary pair consists of a p-type and an n-type transistor, the p-type FET (24, 28) connected at its source to a high voltage reference (Vdd) and at its drain to the drain of the n-type FET (22, 26). The source of the n-type FET (22, 26) is connected to the common drain connections of the next lower-level complementary pair (10, 12), or to a low voltage reference (GND). The approach eliminates the need for passive loads, clocked loads or complementary signals, since each node is actively held high or low.