PARALLEL DESCRAMBLING CIRCUIT AND PARALLEL DESCRAMBLING CIRCUIT

摘要

PURPOSE:To enable accurate randomization by executing inversion at every other bit and scrambling a parallel input even when input digital data is constituted of successive '1' or '0' bits. CONSTITUTION:An inverter 501 is provided on the stages of parallel data V1, V3, V5, and V7 among input stages of the parallel scrambling circuit. Therefore, even when '1' or '0' bits continue in parallel data V0-V7, the inverter 501 inverters them, so the parallel data alternate between '1' and '0' and are made random by circuits following the input stages, thereby securing the approximation of the mark rate in the specific time to 50%. Consequently, the data randomization is performed accurately.