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Cascade assembly of transistors in parallel realised in hybrid circuit technology
Cascade assembly of transistors in parallel realised in hybrid circuit technology
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机译:用混合电路技术实现晶体管的级联并联
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摘要
This mounting is such that the semiconductor chips forming the different transistors of this circuit are organized in a matrix in which the various columns are formed on a first network of conductive tracks and separated by a second and a third arrays of conductive tracks, said networks being respectively connected to the different bonding pads of semiconductor chips.
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