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High-Performance Bipolar Differential Sense Amplifier in BICMOS SRAM
High-Performance Bipolar Differential Sense Amplifier in BICMOS SRAM
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机译:BICMOS SRAM中的高性能双极性差分读出放大器
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摘要
A sensing and decoding scheme layout for a memory device comprising an array made up of columns and rows of memory cells is disclosed wherein sense amplifiers and pairs of memory cell columns are positioned so as to collectively fit within the pitches of the memory cells of the memory cell column pairs and where the sense amplifiers are connected in a one-to-one correspondence with columns of the memory cells.
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