LATCH CIRCUIT AND FLIP-FLOP CIRCUIT APPROPRIATE FOR LOW VOLTAGE OPERATION AND MICROPROCESSOR USING THEM

摘要

PURPOSE:To provide a latch circuit and a flip-flop circuit using a BiCMOS which is appropriate for a high speed operation at low power supply voltage and which has small power consumption and a microprocessor using them. CONSTITUTION:An npn transistor Q1 between a power supply Vcc and an output terminal DO and an npn transistor Q2 between an output terminal DO and a ground GND are provided. A pMOS MP1 and 2 between the Vcc and a base N1 of the Q1, a pM0S MP5 between the Vcc and a base N3 of the Q2, and nMOS MN 3 and 4, inverters MP8 and MN9 inputting an output signal and clocked inverters MP6, MP7, MN7 and MN8 between a gate N2 of the MP5 and the GND are provided. The gate of the MPI and the gate of the MN4 are connected, an input signal DI is supplied to the connection point, and control signals CK and CKN are supplied to the gates of the MP2 and the MN3.