Low-voltage ECL D latch circuit and ECL D flip-flop using it

摘要

The present invention relates to a high-speed ECL D latch circuit operable at a low voltage and an ECL D flip-flop using the same.;The ECL D latch circuit of the present invention includes a first input terminal for inputting input data having a first center level from the outside, a second input terminal for inputting inverted input data having a first center level from the outside, A third input terminal for inputting a clock signal having a center level of 2, a first output terminal for outputting an output signal, a second output terminal for outputting an inverted output signal, And outputs the inverted output signal and the inverted output signal through a first output terminal and a second output terminal, respectively, at a falling edge of the clock signal, and a second output terminal for outputting an inverted output signal from the input terminal through the first output terminal and the second output terminal, respectively The output signal and the inverted output signal are input at the rising edge of the clock signal and the output signal and the inverted output signal are latched until the next falling edge of the clock signal A driving unit for driving the latch unit from a rising edge to a falling edge of the clock signal, and a current source connected to the input unit and the driving unit, respectively.