ECL D LATCH CIRCUIT AND ECL D FLIP-FLOP UTILIZING THE SAME

摘要

PROBLEM TO BE SOLVED: To enable operating at high speed and at a low voltage by outputting input data and inverted input data at the lowering edge of clock signals, inputting output signals and inverted output signals at the rising edge of the clock signals and latching the output signals and the inverted output signals until the next lowering edge of the clock signals. ;SOLUTION: An input part 210 inputs the input data and the inverted input data provided with a center level from input terminals IN21 and IN22 and outputs the output signals and the inverted output signals to output terminals OUT21 and 0UT22 at the lowering edge of the clock signals CK, provided with the center level higher than the center level. Also, a driving part 230 drives a latch part 220 from the rising edge of the clock signals CK to the next lowering edge. Then, the latch part 220 inputs the output signals and the inverted output signals outputted from the input part 210 to the output terminals OUT21 and OUT22 at the rising edge of the clock signals CK and latches the output signals and the inverted output signals until the next lowering edge of the clock signals CK.;COPYRIGHT: (C)1998,JPO