首页> 外国专利> ELECTROSTATIC RESISTANCE INCREASING LATERAL P-N-P TRANSISTOR UTILIZING LATCH VOLTAGE OF N-P-N TRANSISTOR

ELECTROSTATIC RESISTANCE INCREASING LATERAL P-N-P TRANSISTOR UTILIZING LATCH VOLTAGE OF N-P-N TRANSISTOR

机译:利用N-P-N晶体管的闩锁电压增加侧向P-N-P晶体管的静电电阻

摘要

PURPOSE: To improve electrostatic resistance by separately including an n+ - diffusion layer, into a diffusion layer for an emitter and a collector. CONSTITUTION: A P- -base layer 10, an n+ -buried layer 11, and an n- -epitaxial layer 12 are formed successively, a P-diffusion layer 13 for emitter, a P-diffusion layer 14 for collector, and an n+ -diffusion layer 15 for base are formed in the n- -epitaxial layer 12, an n+ -diffusion layer 20 is formed in the diffusion layer 14 for collector, thus connecting a collector electrode 14', and forming a discharge path by the latch voltage of an NPN transistor Q12 . Electrostatic resistance is higher in the case of the latch voltage of the NPN transistor Q12 , as compared with the discharge path of the breakdown voltage of a PNP transistor Q11 . Therefore, a circuit operation operates with a lateral PNP transistor, thus improving the electrostatic resistance.
机译:用途:为了通过将n +扩散层分别包括在用于发射极和集电极的扩散层中来提高静电抵抗力。组成:AP-基层10,n +埋层11和n-外延层12依次形成,用于发射极的P扩散层13,P扩散层14在n-外延层12中形成用于基底的n +-扩散层15,在n-外延层12中形成用于基底的n +-扩散层15,在n-外延层14中形成n +-扩散层20,从而连接集电极电极14’,并通过NPN晶体管Q12的锁存电压形成放电路径。与PNP晶体管Q11的击穿电压的放电路径相比,在NPN晶体管Q12的锁存电压的情况下,静电电阻更高。因此,电路操作通过横向PNP晶体管进行操作,从而改善了静电电阻。

著录项

  • 公开/公告号JPH0483374A

    专利类型

  • 公开/公告日1992-03-17

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRON CO LTD;

    申请/专利号JP19900402505

  • 发明设计人 I HO JIN;

    申请日1990-12-14

  • 分类号H01L29/73;H01L21/331;H01L21/8228;H01L27/082;H01L29/72;H01L29/732;H01L29/735;H01L29/80;H03F1/52;

  • 国家 JP

  • 入库时间 2022-08-22 05:38:29

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