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DEVICE FOR CONECTING MICROPROCESSOR Z80 WITH MICROCOMPUTER HIGHWAY USING COMMON DYNAMIC MEMORY

机译:使用通用动态内存将微处理机Z80与微机高速公路连接的装置

摘要

The device is applied in computing equipment. It gives the opportunity for work with chips, carrying dynamic memory of above 64kbits, requiring 256 refreshment cycles. The device contains a block Arbiter (1) navigating the access to a general dynamic memory (2) connected to navigating outlets (9,10,11,12) with an outlet "readiness of the compound memory" (15) via the first address rim (3) and address lines to a microcomputer highway (4) navigated by a microcomputer highway (4) managed by a microcomputer (5). Part of the address lines are connected with the first address multiplexor (6), while Arbiter block (1) via first navigating rim (13) is connected also with navigating outlets for microprocessor Z80 (14). The microprocessor Z80 (14) is connected via its address lines A0 to A6 and A8 to A15 (29) with a second address multiplexor (7), while via A6 (30), A7 (32) and through navigating outlets (33 and 34) - with a block for formation of a modificated address (31), whose outlet (35) is connected with the second address multiplexor (7). The outlets of both multiplexors (6 and 7) form a multiplexed address rim (8), connected with its address plugs to the general memory (2). The navigating plugs of the address multiplexors (6 and 7) are connected with outlets (18,19 and 28) to the Arbiter block (1), whose outlets (20,21 and 22) are connected via navigating plugs of the compound dynamic memory (2). Other outlets (26 and 27) of the Arbiter block (1) are connected with the plugs for navigation of a two-way data buffer (24), connected from one side (25) with the microcomputer highway (4), while on the other side (23) - with the general dynamic memory (2) and the microprocessor Z80 (14). Outlets (16 and 17) of the Arbiter block (1) are connected with navigation plugs of microprocessor Z80 (14).
机译:该设备应用于计算设备。它提供了使用芯片的机会,该芯片可承载64kbit以上的动态内存,需要256个刷新周期。该设备包含一个仲裁器(1)块,用于访问对通用动态存储器(2)的访问,该存储器与通过第一个地址的出口“复合存储器的就绪状态”(15)的导航出口(9,10,11,12)连接边缘(3)和到由微计算机(5)管理的微计算机高速公路(4)导航的微计算机高速公路(4)的地址线。部分地址线与第一地址多路复用器(6)连接,而仲裁器模块(1)通过第一导航边缘(13)也与微处理器Z80(14)的导航出口连接。微处理器Z80(14)通过其地址线A0至A6和A8至A15(29)与第二个地址多路复用器(7)连接,同时通过A6(30),A7(32)以及导航出口(33和34)连接)-具有用于形成修改的地址(31)的块,其地址(35)与第二地址多路复用器(7)连接。两个多路复用器(6和7)的出口形成一个多路复用的地址边缘(8),其地址插头连接到通用存储器(2)。地址多路复用器(6和7)的导航插头通过插座(18,19和28)连接到仲裁器模块(1),仲裁器模块的插座(20,21和22)通过复合动态存储器的导航插头连接(2)。仲裁器模块(1)的其他插座(26和27)与用于导航双向数据缓冲区(24)的插头连接,该插头从一侧(25)与微型计算机高速公路(4)连接,而在另一面(23)-带有通用动态存储器(2)和微处理器Z80(14)。仲裁器模块(1)的出口(16和17)与微处理器Z80(14)的导航插头连接。

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