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Large-scale integrated circuit device such as a wafer scale memory having improved arrangements for bypassing, redundancy, and unit integrated circuit interconnection
Large-scale integrated circuit device such as a wafer scale memory having improved arrangements for bypassing, redundancy, and unit integrated circuit interconnection
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机译:大规模集成电路器件,例如晶圆级存储器,具有改进的旁路,冗余和单元集成电路互连的布置
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摘要
A plurality of unit integrated circuits mounted on a large- scale integrated circuit device, for example, a wafer scale memory, are each provided with a bypass circuit which selectively shorts input and output nodes in the corresponding unit integrated circuit. By selectively bringing the bypass circuit into a transfer state, it is possible to effectively couple together all unit integrated circuits which are judged to be normal among a plurality of unit integrated circuits disposed along one row, for example. Improved redundancy arrangements are also provided, including first and second redundant elements for the unit integrated circuits, to effectively utilize the normal elements in the unit integrated circuits. Further, an improved arrangement for hierarchically connecting together the outputs of all the unit circuit blocks is provided which reduces the signal line load for the memory device.
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