Semiconductor integrated circuit device having a gate array with a RAM and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array

摘要

In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.