A current mode sample-and-hold circuit 46, includes a differential amplifier 20, having a non-inverting input coupled to a first leg of a current mirror 39, from which a first current 11 to be sampled is drawn. An inverting input of the differential amplifier 20, is coupled to its output and further coupled to a capacitor 36, through a sample hold switch 32. The first current 11 drawn from the first leg of the current mirror 39, causes the capacitor 36, to charge through the differential amplifier, when the switch 32 is closed. The charged capacitor is coupled to the current mirror and biases the current mirror so as to provide the required first current. Opening the sample hold switch 32 causes the capacitor 36 to maintain a bias level determined by the first current. The bias signal in turn causes a mirrored current lOUT flowing in a second leg of the current mirror to be maintained, even in the absence of the first current. Thus an input current is sampled and a corresponding output current is provided. The capacitor operates in a feedback loop to improve accuracy. Furthermore, the capacitor is isolated from both the input and output providing high frequency capability.
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