首页> 外国专利> Semiconductor integrated circuit device having additional capacitor effectively decreasing parasitic capacitance coupled with resistor

Semiconductor integrated circuit device having additional capacitor effectively decreasing parasitic capacitance coupled with resistor

机译:具有附加电容器的半导体集成电路器件,该电容器有效地减小了与电阻器耦合的寄生电容

摘要

A semiconductor integrated circuit device is fabricated on a semiconductor substrate (11) having a lightly doped p-type silicon bulk (11a) and a lightly doped n-type epitaxial layer (11b), and a resistor is formed on a field oxide film (12) grown on the lightly doped n-type epitaxial layer, wherein a trench isolation (13a/ 13b/ 14a/ 14b) penetrates from the field oxide film into the lightly doped p-type silicon bulk for allowing a part (11c) of the lightly doped epitaxial layer under the resistor to enter electrically isolating state, thereby decreasing parasitic capacitance coupled with the resistor by virtue of an additional junction capacitor coupled in series therewith.
机译:在具有轻掺杂的p型硅块(11a)和轻掺杂的n型外延层(11b)的半导体衬底(11)上制造半导体集成电路器件,并在场氧化膜( 12)生长在轻掺杂的n型外延层上,其中沟槽隔离(13a / 13b / 14a / 14b)从场氧化膜穿透到轻掺杂的p型硅块中,以允许部分(11c)电阻器下面的轻掺杂外延层进入电隔离状态,从而借助于与之串联耦合的附加结电容器来减小与电阻器耦合的寄生电容。

著录项

  • 公开/公告号EP0538807A1

    专利类型

  • 公开/公告日1993-04-28

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号EP19920117949

  • 发明设计人 SHIMIZU JUNZOH;

    申请日1992-10-20

  • 分类号H01L27/06;H01L21/3205;

  • 国家 EP

  • 入库时间 2022-08-22 05:05:40

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