A multiple node computer system includes processor nodes, memory nodes, and input/output nodes interconnected on a pended bus (25). The system includes a lockout indicator (240) which is set upon receipt of a locked response message by a processor node from a memory node in response to an interlock read command. The processors include a lockout check circuit (250) responsive to the condition of the lockout indicator (240) and will restrict generation of additional interlock read commands according to a predetermined access gating criterion until the lockout indicator is reset. In this manner, processor nodes of the system are assured equitable access to a memory node.
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