Power FET mfr. using angled ion implantation beam - forming asymmetrical insulation zone in contact layer applied to surface of channel layer beneath gate metallisation

摘要

The power FET, having a channel layer (1) and highly doped source and drain contact layers (2) with an applied metallisation, is mfd. by initial formation of the channel layer (1) on the surface of a semiconductor wafer, followed by formation of the contact layer (2) and an auxiliary dielectric layer (4). The latter is etched via a mask for exposing the area of the contact layer (2) used for the transistor gate, prior to ion implantation via an ion implantation beam at an angle to the surface of the contact layer (2), to provide an asymmetrical insulation zone (11). The gate metallisation insulated from the source and drain metallisation is provided via a spacer technique. ADVANTAGE - Ensures min. source resistance and min. gate-drain capacitance, for high power and low noise.