Integrated semiconductor memory circuit with complementary MOS inverters in latch circuit - allows setting and resetting of flip=flop function by signals applied to source of N-channel MOSFET

摘要

A data locking circuit (9) is formed by two inverters comprising a p-channel MOSFET (16) and an n-channel MOSFET (15). The source connection of the latter is linked to a reset signal input (7) which addresses an inverter (2) through the n-channel MOSFET so as to reset the data locking circuit. The data input (5) is clocked (4) through another n-channel MOSFET (10) to a common connection (20) of the gate electrodes of both transistors (15, 16) and the output is inverted (3). ADVANTAGE - Set/reset function is more easily incorporated in circuit with fewer transistors and reduces vol. of circuit package.