Circuit with row redundancy for semiconductor memory device for repairing or replacing a defective cell of a memory cell array

摘要

a) Circuit with row redundancy for semiconductor memory device. b) The circuit is characterised in that it comprises: - an address selector (300) intended for receiving two or more pairs of address bits designating the defective cell, and for selecting one of these two or more address bits; - a fuse box (100) intended for receiving the group of pairs of address bits and for storing the information of the other address bits, except for the bit pair selected in the address selector; and - at least one decoder with redundancy (200) intended for decoding the output signals from the address selector (300) and from the fuse box (100) so as to maximise the efficiency of row redundancy. IMAGE