Fast counter/divider and its use in a swallower counter

摘要

A counter/divider dividing an input frequency (F1) by 2.sup.q+ n +1/2, comprises a first divider by 2.sup.q (30) receiving the signal to divide of a frequency F1 and provides 2.sup.q+1 outputs at the frequency F1/2. sup.q out of phase the ones to the others of 360°/2.sup.q+1 ; a multiplexer (32) having a control terminal (34) and sequentially providng at its output (33) each of said 2.sup.q+1 outputs each time a control signal is applied; and a second divider by 2.sup.n (31) receiving the output (33) of the multiplexer and providing the desired output (34) of the counter/divider, this output being applied to the control terminal of the multiplexer.