CMOS 3-STATE BUFFER CIRCUIT AND CONTROL METHOD THEREFOR

摘要

PURPOSE: To provide a CMOS 3-state buffer circuit and a control method therefor with which the delay of signal is reduced by suppressing counter electromotive force to be induced when turning on a transistor for driving a load. ;CONSTITUTION: Concerning the CMOS 3-state buffer circuit having a driving circuit 30 constituted by serially connecting PMOS and NMOS output transistors so as to supply a driving current to the load, a 1st control circuit 20 for controlling the PMOS transistor of the driving circuit 30 and a 2nd control circuit 10 for controlling the NMOS transistor of the driving circuit 30, further, an auxiliary driving circuit 50 is provided between the gate of the NMOS transistor of the driving circuit 30 and the output of the 2nd control circuit 10, and a voltage lower than a power supply voltage VCC is supplied to the gate of the NMOS transistor of the driving circuit 30 by the output of the auxiliary driving circuit 50.;COPYRIGHT: (C)1994,JPO