首页> 外国专利> PROFILE TAILORED TRENCH ETCH USING A SF_-0_ ETCHING COMPOSITION WHEREIN BOTH ISOTROPIC AND ANISOTROPIC ETCHING IS ACHIEVED BY VARYING THE AMOUNT OF OXYGEN

PROFILE TAILORED TRENCH ETCH USING A SF_-0_ ETCHING COMPOSITION WHEREIN BOTH ISOTROPIC AND ANISOTROPIC ETCHING IS ACHIEVED BY VARYING THE AMOUNT OF OXYGEN

机译:使用SF_-0_蚀刻组成的轮廓沟槽式蚀刻,通过改变氧气量可实现等距和各向异性蚀刻

摘要

PROFILE TAILORED TRENCH ETCH USING ASF6-O2 ETCHING COMPOSITION WHEREINBOTH ISOTROPIC AND ANISOTROPIC ETCHINGIS ACHIEVED BY VARYING THE AMOUNT OF OXYGENABSTRACT OF THE DISCLOSUREA dopant-opaque layer of polysilicon is deposited ongate oxide on the upper substrate surface to serve as a patterndefiner during fabrication of the device. It provides controlover successive P and N doping steps used to create the necessaryoperative junctions within a silicon substrate and the conductivestructures formed atop the substrate. A trench is formed in theupper silicon surface and a source conductive layer is depositedto electrically contact the source region as a gate conductivelayer is deposited atop the gate oxide layer. The trench sidewallis profile tailored using a novel O2-SF6 plasma etch technique.An oxide sidewall spacer is formed on the sides of the patterndefiner and gate oxide structures, before depositing theconductive material. A planarizing layer is applied and used as amask for selectively removing any conductive material depositedatop the oxide spacer. The polysilicon layer on the oxide isreduced in thickness during trenching so that any conductivematerial deposited atop the spacers protrude upward for easyremoval of excess, conductive material. The sidewall spacers canbe sized, either alone or in combination with profile tailoring ofthe trench, to control source-region width (i.e., parasiticpinched base width) and proximity of the source conductor to theFET channel. Electrical contact between the source conductivelayer and the source regions is enhanced by forming a low-resistivity layer between them.
机译:使用A量身定制的风沟SF6-O2蚀刻组合物中各向同性和各向异性通过改变氧气量来实现披露摘要掺杂剂不透明的多晶硅层沉积在衬底上表面上的栅氧化层用作图案设备制造过程中的定义器。提供控制在连续的P和N掺杂步骤中,用于创建必要的硅基板和导电材料内的有效结在衬底顶上形成的结构。沟槽形成在硅上表面和源极导电层沉积与源极区域电接触,作为栅极导电在栅极氧化层的顶部沉积一层硅层。沟槽侧壁使用新颖的O2-SF6等离子蚀刻技术定制的轮廓。在图案的侧面上形成氧化物侧壁间隔物沉积前先定义和栅氧化层结构导电材料。应用平坦化层并将其用作用于选择性去除沉积的任何导电材料的掩模在氧化物隔离层的顶部。氧化物上的多晶硅层是减少开槽期间的厚度,以便任何导电沉积在垫片顶部的材料容易向上突出去除多余的导电材料。侧壁垫片可以可以单独确定尺寸,也可以与沟槽,以控制源区宽度(即寄生收缩的基本宽度)和源导体与FET通道。导电源之间的电接触层和源极区域通过形成低它们之间的电阻率层。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号