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PROFILE TAILORED TRENCH ETCH USING A SF_-0_ ETCHING COMPOSITION WHEREIN BOTH ISOTROPIC AND ANISOTROPIC ETCHING IS ACHIEVED BY VARYING THE AMOUNT OF OXYGEN
PROFILE TAILORED TRENCH ETCH USING A SF_-0_ ETCHING COMPOSITION WHEREIN BOTH ISOTROPIC AND ANISOTROPIC ETCHING IS ACHIEVED BY VARYING THE AMOUNT OF OXYGEN
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机译:使用SF_-0_蚀刻组成的轮廓沟槽式蚀刻,通过改变氧气量可实现等距和各向异性蚀刻
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PROFILE TAILORED TRENCH ETCH USING ASF6-O2 ETCHING COMPOSITION WHEREINBOTH ISOTROPIC AND ANISOTROPIC ETCHINGIS ACHIEVED BY VARYING THE AMOUNT OF OXYGENABSTRACT OF THE DISCLOSUREA dopant-opaque layer of polysilicon is deposited ongate oxide on the upper substrate surface to serve as a patterndefiner during fabrication of the device. It provides controlover successive P and N doping steps used to create the necessaryoperative junctions within a silicon substrate and the conductivestructures formed atop the substrate. A trench is formed in theupper silicon surface and a source conductive layer is depositedto electrically contact the source region as a gate conductivelayer is deposited atop the gate oxide layer. The trench sidewallis profile tailored using a novel O2-SF6 plasma etch technique.An oxide sidewall spacer is formed on the sides of the patterndefiner and gate oxide structures, before depositing theconductive material. A planarizing layer is applied and used as amask for selectively removing any conductive material depositedatop the oxide spacer. The polysilicon layer on the oxide isreduced in thickness during trenching so that any conductivematerial deposited atop the spacers protrude upward for easyremoval of excess, conductive material. The sidewall spacers canbe sized, either alone or in combination with profile tailoring ofthe trench, to control source-region width (i.e., parasiticpinched base width) and proximity of the source conductor to theFET channel. Electrical contact between the source conductivelayer and the source regions is enhanced by forming a low-resistivity layer between them.
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