Organization of an integrated cache unit for flexible usage in supporting multiprocessor operations

摘要

Methods and apparatus are disclosed for realizing an integrated cache unit which may be used to flexibly implement a plurality of multiprocessor support schemes. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip and is programmable. The flexible implementation of the support schemes is achieved, according to the preferred embodiment of the invention, by providing for the setting of internal ICU option bits in on-chip special registers. The setting of these bits translates into the selection of a desired support scheme. The bits may be set under software control and allows a high performance multi­processor cache system to be designed with few parts, at low cost and with the ability to perform with high efficiency.