A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region (15) in a wafer including an epitaxial layer (12) on a substrate (10). A first, heavily doped drain region and bit line element (18) is formed around the trench on the surface of the well (15) , and a second, lightly-doped drain region (24) is formed proximate to the first drain region (18) and self-aligned to the trench sidewalls. A source region (26) is located beneath the trench, which is filled with polysilicon (32), above which is gate and further polysilicon forming a transfer wordline (33). The gate polysilicon (32) is separated from the trench side walls by a layer (30) of gate oxide insulation. The well region (15) at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.
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