A method for fabricating a fully featured high density ' electrically erasable programmable read only memory ' (EEPROM) cell with a polytron spacer

摘要

(EEPROM) " cell is first fabricated by forming the first and second first field oxide (FOX1) regions of the P-well in the N- By defining the first and second buried N ⁺ bit lines in the P-well adjacent to the first and second FOX1 regions, respectively, the P-well channel region is defined between the first and second bit lines. First and second second field oxide (FOX2) regions are respectively formed adjacent to the first and second FOX1 regions and respectively on the first and second buried N ⁺ bit lines, respectively. A gate oxide layer is formed on the P-well between the first and second FOX2 regions to a thickness of 300-500 A. A polysilicon layer is formed on the gate oxide to extend only on the first portion of the P- Then, the tunnel window is defined on the gate oxide on the P-type channel region The gate oxide is removed from the tunnel window and a tunnel oxide is formed in the window to a thickness of approximately 80-100 A. Thereafter, a spacer / contact window is defined on the field oxide and a spacer / contact window is formed on the field oxide phase Contact oxide layer is removed from the spacer / contact window on the floating gate during the tunnel oxide growth, and then a polysilicon tunnel spacer is formed on the tunnel oxide and the spacer / The gate of the floating gate and the gate of the floating gate on the floating gate, and forming an electrical contact with the floating gate at the edge of the floating gate, Floating gate, poly tunnel spacer, and floating gate Finally, a second polysilicon layer is formed on the ONO to define a control gate of the EEPROM cell, thereby forming a second polysilicon layer over the second portion of the channel region Is directly formed on the ONO to define the gate of the internal access transistor of the EEPROM cell.