Bidirectional digital driver stage with for the implementation of a clock-controlled shift register test architecture (boundary scan) shift register cells serving

摘要

A first shift register cells (ASC1), forming a signature, incorporates a conventional cell (BSC) preceded by an input selector (MUX3) supplied with a shift path input (TDI) and an alternative input (AE) from two Exclusive-OR gates (EX1,EX2) and another selector (MUX4). Another cell (ASC2) producing the test pattern operates in two modes whereby either test pattern is applied to internal or external circuitry or the signature is formed from its test responses, according to the control of the driver amplifier (TE) by a third cell (ASCT). ADVANTAGE - Circuit can be tested with temporal efficiency using pseudo-random test pattern.