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Integrated circuit with internal voltage reducer and ageing test mode - transfers voltage corresp. to change in external voltage, to internal supply line in response to ageing mode activation signal

机译:具有内部降压器和老化测试模式的集成电路-传输相应的电压。响应老化模式激活信号,改变内部电源的外部电压

摘要

The integrated circuit contains a power mode control circuit (1), an internal voltage supply reducer circuit (2), internal circuitry (3) and external interface circuitry (4) running at the supply voltage (Vcc). The control circuit switches the voltage reducing circuit to stabilise the internal voltage at Vo when the supply voltage (Vcc) exceeds it. When the supply voltage exceeds a second threshold V1 the internal voltage increases further as the supply voltage Vcc increases. USE/ADVANTAGE - E.g. for DRAMs etc. Only increases internal supply voltage if aging test is necessary. Increases reliability of IC and reduces power consumption.
机译:该集成电路包括电源模式控制电路(1),内部降压电路(2),内部电路(3)和以电源电压(Vcc)运行的外部接口电路(4)。当电源电压(Vcc)超过内部电压时,控制电路切换降压电路以将内部电压稳定在Vo。当电源电压超过第二阈值V1时,内部电压随着电源电压Vcc的增加而进一步增加。使用/优势-例如用于DRAM等。仅在需要进行老化测试时才增加内部电源电压。提高IC的可靠性并降低功耗。

著录项

  • 公开/公告号DE4244555A1

    专利类型

  • 公开/公告日1993-11-18

    原文格式PDF

  • 申请/专利权人 MITSUBISHI DENKI K.K. TOKIO/TOKYO JP;

    申请/专利号DE19924244555

  • 发明设计人 MORI SHIGERU ITAMI HYOGO JP;

    申请日1992-12-31

  • 分类号H01L23/58;H01L27/105;

  • 国家 DE

  • 入库时间 2022-08-22 04:35:53

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