Microwave power FET mfr. - by etching asymmetric gate recess in breakdown voltage controlling recess, to give transistors of high power and gain

摘要

Mfr. of a microwave power FET, having a substrate (1) supporting active and contact semiconductor layers (2,3), two source (4) and drain (5) metallisations and a gate metallisation (18), involves, (a) etching a first recess (12) in the contact layer (3), between the source and drain metallisations, (4,5); and (b) etching a second recess (17) in the active layer (2) within the first recess (12) and at an asymmetrical position nearer the source metallisation (4) than the drain metallisation (5), the gate metallisation (19) being located in the second recess (17). Length of the first recess (12) controls the breakdown voltage (VBK) of the transistor and the depth of the second recess (17) controls the current (KDS) passing through the transistor. First recess is formed by depositing a dielectric layer on the structure, depositing a masking resin layer, forming a mask opening at the first recess location symmetrically between the source and drain, etching the dielectric layer at the mask opening location, etching the first recess (12) and dissolving the resin mask and the dielectric. Second recess is formed in a similar manner except that it is located nearer the source (14) than the drain (5) and that it has a length equal to the gate length. Finally, a gate metallisation (18) is deposited in the second recess (17). ADVANTAGE - Process is simple and allows mfr. of microwave transitions with high power and high gain.