A high level controller for maintaining communication with a host processor via a host processor interface for establishing communication paths between the host processor interface, an internal processor and a plurality of storage means. A first means receives indicia from the internal processor where the indicia specifies one of the communication paths and generates control signals for forming the specific communication path requested. A second means receives the control signals from the first means and forms the requested communication path. A third means is connected to the first and second means for controlling the communication of the system with the host processor interface in accordance with control signals generated by the first means. In this manner various data paths for communication between the host interface, internal processor and a plurality of storage means may be adaptably specified and formed to make optimum use of the system.
展开▼
