首页>
外国专利>
Delay test coverage enhancement for logic circuitry employing level sensitive scan design
Delay test coverage enhancement for logic circuitry employing level sensitive scan design
展开▼
机译:采用电平敏感扫描设计的逻辑电路的延迟测试覆盖率增强
展开▼
页面导航
摘要
著录项
相似文献
摘要
By selectively associating output signal lines with logic circuit input signal lines, it is possible to produce a combination logic circuit and latch string in which no pair of adjacent latches is connected to the same cone of logic in the logic circuit. This provides greatly improved capabilities for delay or AC circuit test with respect to the independence of test pairs of excitation data. The objective may also be achieved in whole or in part through the use of dummy latch elements which do not feed any logic circuit input signal lines.
展开▼