An integrated hardware generator for generating digital signals representative of vectors, polygons and conics primitives and area fills therefor. The primitive signals are used in the formation of a final digital output signal read into a bit map memory of a graphics display processor. Its operation is based on applying one or more of a set of internal subfunctions to generate mathematical solutions for rendering each geometric shape as a graphics primitive digital signal. The basic building block of the generator is a digital differential analyzer which is adapted to accumulate fractional (subpixel) components of x/y coordinate data and to signal when the accumulation overflows across pixel boundaries. This occurrence enables an increment or decrement of the x/y coordinates that indicate the pixel address to be loaded (drawn). The digital differential analyzer forms an independent vector generator and comprises a pair of input differential multiplexers, an arithmetic logic unit and a register file. On receipt of a command from a host processor the multiplexers receive parameters that specify the primitive to be drawn and select the appropriate parameters for input to the arithmetic logic unit. The arithmetic logic unit accumulates parameters and stores the results in the register file. The output of the register file is fed back to the multiplexers to provide inputs fr the next operation.
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