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Single poly EE cell with separate read/write paths and reduced product term coupling

机译:具有独立读/写路径和减少乘积项耦合的单个poly EE单元

摘要

A single poly EE cell and an array using said cell, with the array being provided electrical connections such that the select gate for the read select transistor and the select gate for the write select transistor may be separately controlled. In the array, first level metal is utilized for connection to the gates of the read and write select transistors and second level metal is utilized for connection to the product term connections of the cell.
机译:单个poly EE单元和使用所述单元的阵列,该阵列被提供电连接,使得可以分别控制用于读取选择晶体管的选择栅极和用于写入选择晶体管的选择栅极。在阵列中,第一级金属用于连接到读取和写入选择晶体管的栅极,第二级金属用于连接到单元的乘积项连接。

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