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dainamitsuku die memory storage

机译:达南筑波纪念曲

摘要

PURPOSE:To prevent an abnormal current from that may occur immediately after the turning on of a power source by inactivating a chip activating signal inside a chip for a determined time following the turning on the power source. CONSTITUTION:At a moment immediately after the rising of a power supply voltage, the nodes A, A' of a CR circuit constituted of a capacitor C and a resistor R is in a low level. Then, the capacitor C is charged through the resistor R, and until a time when this voltage exceeds the threshold of a waveform shaping circuit G1, and output Q from an order circuit consisting of a NAND gate G2 and an OR gate G keeps its being in a high level regardless of the input level the inverse of a raw address strobing signal RAS. Accordingly, for such a period as corresponding to the capacitor C, the resistor R, and the threshold of the circuit G1, chip activating signals are automatically inactivated, hence an abnormal current immediately after the turning on of the power source can be prevented.
机译:目的:为防止在接通电源后立即在确定的时间内使芯片内部的芯片激活信号处于非激活状态,可能会出现异常电流。组成:在电源电压升高之后的瞬间,由电容器C和电阻器R组成的CR电路的节点A,A'处于低电平。然后,电容器C通过电阻器R充电,直到该电压超过波形整形电路G1的阈值为止,并且从由与非门G2和或门G组成的阶跃电路的输出Q保持为无论输入电平如何,在高电平时,原始地址选通信号RAS的反相。因此,在与电容器C,电阻器R和电路G1的阈值相对应的时间段内,芯片激活信号被自动去激活,因此可以防止刚接通电源之后的异常电流。

著录项

  • 公开/公告号JPH0789434B2

    专利类型

  • 公开/公告日1995-09-27

    原文格式PDF

  • 申请/专利权人 日本電気株式会社;

    申请/专利号JP19860270124

  • 发明设计人 東 常昭;

    申请日1986-11-12

  • 分类号G11C11/401;G11C11/41;G11C11/413;

  • 国家 JP

  • 入库时间 2022-08-22 04:27:31

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