PURPOSE:To accurately detect a frequency error, by detecting a phase correcting direction just before and immediately after the self-propelling of a D (digital) PLL, and adding correction on the detected result of the frequency error. CONSTITUTION:A control direction detecting means 2 detects a phase control direction just before and immediately after the selfpropelling period of the DPLL circuit 1 by a reception clock TC corresponding to a reception signal TP, and a reproducing clock RC generated from the circuit 1. The output of the circuit 2 is sent to an initial convergence detecting means 3, and detects the fact that the first pull-in of the circuit 1 is completed. After the first convergence, a self-propelling executing means 4 makes the circuit 1 self propel. thereby, preventing phase correction. After the lapse of the self-propelling period, the frequency error is generated again. A quantity to be corrected for the frequency error is decided based on the clock TC and the detected output of the means 2 by a frequency error correcting means 5. Based on the frequency error, the circuit 1 is phase-controlled compulsorily without receiving the reception clock.
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