CONVOLUTION ENCODER AND TRELLIS ENCODING MODULATION SYSTEM

摘要

PURPOSE: To simplify circuit realization and integration by constituting a convolution encoder of the connection type of modulo two sum by three memory elements and a generation polynomial. ;CONSTITUTION: A first bit 306 among three bit output signals is the modulo two sum value of a present bit input 301 in an upper stage, input bit delayed twice in the upper stage, that is, input bit 304 before two system clocks, and residual present input bit 302 in a lower stage, and input bit 305 delayed once in the lower stage, that is, input bit before one system clock. A second bit 307 is the modulo two sum value of an input bit 303 delayed once in the upper stage, input bit 304 delayed twice, and present input bit 302 in the lower stage. A third output bit 308 is the modulo two sum value of the present input bit 301 in the upper stage and the input bit 305 delayed once in the lower stage.;COPYRIGHT: (C)1995,JPO