ERROR ALLOWANCE SYNCHRONOUS LETTER DETECTING SYSTEM AND ERROR ALLOWING METHOD

摘要

PURPOSE: To detect a synchronous letter by connecting a comparing circuit to the display of an estimated multiple bit synchronous letter or mark and those of a receiving multiple bit, issuing a correct coincidence judging signal with a precise detection comparing circuit and combining the output of a relaxation type comparing circuit via an OR gate. ;CONSTITUTION: Data are connected to a main CPU 10 from a head 28 using a track logic 40 via the reading/writing control part 24 of a recording device 20. The output of the logic 40 is sent to a synchronous letter detection voting logic 50. Further, a relaxation type detecting mode is realized using that the emergence of the synchronous letter is displayed with the logic 50. Also a control logic 60 is provided with, and a relaxation type synchronous letter detecting function is allowed or inhibited using the command of a command device 16. This is executed by generating a relaxation type synchronous letter detecting bit combined with the synchronous letter detecting circuit. The identification is executed in response to a correct coincidence between a prospected multiple bit and anticipated synchronous letter or the coincidence of allowance wherein the difference does not exceed the error of two or less adjacent bits.;COPYRIGHT: (C)1995,JPO