Method and arrangement for generation of transmission multiplex signal and for synchronization of a reception multiplex signal on the transmission multiplex signal

摘要

In the plesiochronous digital hierarchy, digital signals of one level only have approximately the same clock frequencies and are therefore processed plesiochronously throughout. However, synchronous operation of transmitted and received multiplex signal are also required. This is possible if auxiliary frames are generated in the transmitting and receiving section of a device, into which frames dummy bits (LB) are inserted in between the data bytes (SD) (Figure 2). These dummy bits are eliminated with the cooperation of a common auxiliary clock in serial/parallel conversion (Figure 3), storage and parallel/serial conversion (Figure 4). The receiving clock is in each case aligned with the transmitting clock by adding or removing one or a number of dummy bits between two data bytes (SD) in the receiving section. IMAGE