RATE CONVERSION CIRCUIT TO INTERFACE T1 TRANSMISSION LINE AND E1H TRANSMISSION LINE

摘要

The converter comprises a first clock recovering unit, a data outputting unit, a T1 line clock generating unit, a E1H/T1 convert buffer, a FIFO read clock generating unit, a first T1 transzceiver, a second clock recovering unit, a second T1 transceiver, a E1H line transmission clock generating unit, a FIFO light clock generating unit, and a T1/E1H convert buffer.