A decimating filter comprising a multiplexer (1) which is supplied with signal values (xi) at a predetermined sampling rate (1/T) and which outputs signal values at half the sampling rate via two outputs (3, 5). These outputs (3, 5) are connected for each significant position of the p-digit binary filter coefficients (c6 to c1) to separate bit-specific circuits (bit planes) (BP1, BP2) which in each case contain the partial-product stages (Mc60...Mc10, Mc61...Mc11) of all filter coefficient bits of a particular significance and an adder-register chain circuit (8...30, 8'...30') associated with these bits. The output (30') of the chain circuit of the most significant bit plane (BP2) represents the filter output. …IMAGE…
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