Process for selectively etching integrated circuit devices having deep trenches or troughs or elevated features with re-entrant profiles

摘要

An improved process for selectively etching integrated circuit devices having deep trenches or troughs or elevated features with re- entrant profiles is disclosed. The process is capable of producing photoresist patterns having line and space dimensions which are less than 3 microns. Such patterns may be employed to produce high-resolution etched patterns within the functional layers comprising those circuits. The process proceeds without the formation of unwanted residual photoresist material in deep trenches and troughs and in recesses along the sidewalls of raised features having re-entrant sidewall profiles. No auxiliary, critical-dimension-shrinking etch step is required to remove such residual photoresist in those locations. The process is particularly useful for in-process integrated circuit having either a plurality of elevated features or a plurality of trenches or troughs, in combination with at least one conductivity-providing layer, which covers the raised features or lines the trenches or troughs. The process involves forming an etch mask pattern on the in-process circuit using negative photoresist as the mask material, with the pattern covering certain portions of the conductivity-providing layer and exposing other portions of the conductivity-providing layer. The exposed portions of the conductivity- providing layer are then etched.