首页> 外国专利> Bipolar transistor with a self-aligned heavily doped collector region and base link regions.

Bipolar transistor with a self-aligned heavily doped collector region and base link regions.

机译:具有自对准重掺杂集电极区和基极链接区的双极晶体管。

摘要

A process is provided for forming a bipolar transistor and a structure thereof. In particular a single polysilicon self-aligned process for a bipolar transistor having a polysilicon emitter is provided. A sacrificial layer defining an opening is provided in a device well region of a substrate, and, after forming a self-aligned base region within the opening, emitter material is selectively provided in the opening to form an emitter-base junction. The sacrificial layer functions as a mask for ion implantations to form the base region, and if required, an underlying local collector region. The sacrificial layer is removed, to expose the well region adjacent sidewalls of the emitter structure. A self-aligned link region implant may be performed before forming isolation on exposed sidewalls of the emitter structure. Extrinsic base contacts are formed in the surface of the surrounding well region. The sacrificial layer is preferably a material which may be removed by an etch process with high selectivity to the substrate to avoid damage on overetching, for improved manufacturability and reliability. The process flow is compatible with CMOS processing, and applicable to bipolar CMOS integrated circuits.
机译:提供了一种用于形成双极晶体管的工艺及其结构。特别地,提供了用于具有多晶硅发射极的双极晶体管的单多晶硅自对准工艺。在衬底的器件阱区中提供限定开口的牺牲层,并且在开口中形成自对准基极区之后,在开口中选择性地提供发射极材料以形成发射极-基极结。牺牲层用作离子注入的掩模,以形成基极区,如果需要,还可以形成下面的局部集电极区。去除牺牲层,以暴露出与发射极结构的侧壁相邻的阱区。可以在发射极结构的暴露侧壁上形成隔离之前执行自对准链接区注入。外在的基极接触形成在周围的阱区域的表面中。为了提高可制造性和可靠性,牺牲层优选地是可以通过对衬底具有高选择性的蚀刻工艺来去除的材料,以避免对过蚀刻的损害。该处理流程与CMOS处理兼容,并且适用于双极CMOS集成电路。

著录项

  • 公开/公告号US5428243A

    专利类型

  • 公开/公告日1995-06-27

    原文格式PDF

  • 申请/专利权人 NORTHERN TELECOM LIMITED;

    申请/专利号US19930158544

  • 发明设计人 IAN W. WYLIE;

    申请日1993-11-29

  • 分类号H01L29/73;H01L29/46;

  • 国家 US

  • 入库时间 2022-08-22 04:04:44

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