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Transistor arrangement for forming basic cell of master-slice type semiconductor integrated circuit device and master-slice type semiconductor integrated circuit device

机译:用于形成主片型半导体集成电路器件的基本单元的晶体管布置和主片型半导体集成电路器件

摘要

A master-slice type semiconductor integrated circuit device includes a first transistor, and a second transistor. The first and second transistors are arranged side by side in a first direction. The first and second transistors respectively have first and second gate electrodes extending in a second direction perpendicular to the first direction. The first gate electrode has a first portion in which two gate contacts arranged in the first direction can be made. The second gate electrode has a second portion in which two gate contacts arranged in the first direction can be made.
机译:主片型半导体集成电路器件包括第一晶体管和第二晶体管。第一和第二晶体管在第一方向上并排布置。第一和第二晶体管分别具有在垂直于第一方向的第二方向上延伸的第一和第二栅电极。第一栅电极具有第一部分,在该第一部分中可以形成沿第一方向布置的两个栅触点。第二栅电极具有第二部分,在该第二部分中可以形成沿第一方向布置的两个栅触点。

著录项

  • 公开/公告号US5436485A

    专利类型

  • 公开/公告日1995-07-25

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US19940365173

  • 申请日1994-12-28

  • 分类号H01L27/02;H01L27/10;

  • 国家 US

  • 入库时间 2022-08-22 04:04:36

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