首页>
外国专利>
Exploiting multi-cycle false paths in the performance optimization of sequential circuits
Exploiting multi-cycle false paths in the performance optimization of sequential circuits
展开▼
机译:在时序电路性能优化中利用多周期错误路径
展开▼
页面导航
摘要
著录项
相似文献
摘要
A methodology for the redesign of sequential VLSI circuits to increase the circuit speed involves cascading the circuit over a plurality of time frames without the memory elements, identifying any long false paths in the cascaded circuit, reconfiguring the original circuit to eliminate the false paths while providing fanout to preserve functionality, and retiming the reconfigured circuit to reduce circuit delay.
展开▼