PURPOSE:To heighten the detecting accuracy of an error without increasing redundancy, by re-arranging the order of bits included in an address signal, and a redundancy code formed based on the address signal, and adding them at every a prescribed length of data. CONSTITUTION:The address signal AD of n-bits from an address generation circuit 1 is supplied to a rearranging circuit 4, and an inverter 3. At the inverter 3, the bit of the signal AD is inverted, and is supplied to the rearranging circuit 4 as the redundancy code AD'. At the rearranging circuit 4, the position of each bit of a parallel input of 2n-bits is changed according to a prescribed conversion rule, and a parallel output of 2n-bits is generated. The parallel output is converted to a serial data (AD+AD') by a parallel/serial conversion circuit 5. The signal (AD+AD') is added on the forefront of each block of the data by an adder circuit 6. In this way, it is possible to heighten the detecting accuracy of the error without increasing the redundancy.
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