METHOD OF FORMATION OF SINGLE TRANSISTOR MEMORY CELL STRUCTURE AND SELF-ALIGNED SINGLE TRANSISTOR MEMORY CELL STRUCTURE

摘要

PROBLEM TO BE SOLVED: To provide a single transistor flash EEPROM cell structure which is improved in order that the dimension of effective channel length be independent of the critical dimensions of a stacked gate structure, and to provide a manufacturing method of the cell structure. ;SOLUTION: A cell structure 210 contains an n^--embedded channel/junction region 216 which is injected into a substrate 212 before the formation of a tunnel oxide film 226 and a stacked gate structure 234. After the stacked gate structure has been formed, a p^--type drain region 222 is injected into the substrate at a large tilt angle. Then, an n⁺-source region 218 and an n⁺-drain region 224 are injected into the substrate in such a manner that they are self-aligned to the stacked gate structure. The cell structure 210 facilitates the scalability for smaller sizes, and is effective for high density application.;COPYRIGHT: (C)1996,JPO